1. Field of the Invention
This invention relates generally to a high performance microprocessor architecture and, more particularly to a high performance microprocessor address bus architecture.
2. Discussion of the Related Art
FIG. 1 shows a typical prior art address bus architecture 100 which includes a mux 102 to select between an address ADDR.sub.-- CPU, indicated at 104, generated by a CPU (central processing unit-not shown) and an address ADDR.sub.-- DMA, indicated at 106, generated by a DMA (direct memory access device-not shown). A select input 108 from a bus master selects which address is output onto the address bus (ADDR) 110. Also shown are peripherals that are connected to address bus 110. The peripherals include an SCU (a serial communications unit) 112, a DMA (a direct memory access unit) 114, a WDT (watchdog timer) 116, a TMR (a timer unit) 118, and a PMU (power management unit) 120. As is known in the computer art an address contains specific information that "notifies" a targeted peripheral that the peripheral has information that needs to be placed on a data path (not shown) for use by other components in the computer.
The prior art devices, as represented by the device shown in FIG. 1, are adequate for those instances when the memory unit has a given memory architecture, that is, a given number of bits to address a location in the memory. However, when it is desired to address other memory architectures, the prior art devices were unable to address them. As is known in the computer art, memory devices which can be made up of DRAM (dynamic random access memory) in which the address input is made up of a row address and a column address, are manufactured with different architectures. For example, some have a nine bit row address and a nine bit column address, others have a ten bit row address and a ten bit column address, and others could have a ten bit row address and an eleven bit column address. As can be appreciated, the prior art device shown in FIG. 1 could not address any DRAM architecture.
In addition, the prior art devices, represented by the device shown in FIG. 1, are incapable of addressing a different size memory, that is, information or data stored in an eight bit data size memory if the CPU or DMA only generates memory addresses based upon the presumption that the information or data is stored in 16 bit data size memory.
Furthermore, the prior art devices, represented by the device shown in FIG. 1, are incapable of adapting if the CPU is in a next address pipeline addressing mode. The prior art device, for example, would latch the next address to the bus before the memory was ready for it.
What is needed, therefore, is an address bus architecture that is (1) capable of addressing different size DRAM architectures, that is (2) capable of addressing different size memory, for example, eight bit memory locations as well as sixteen bit memory locations, that is (3) capable of handling memory addresses when the CPU is in a next address pipelining mode, and that is (4) capable of testing the core memory independently.
The inventors designed a computer architecture that involved the integration of a 386 core processor with many on-chip peripherals. One of the design goals was for the 386 microprocessor to be able to perform memory cycles at 33 MHz and V.sub.cc =5 volts made in CS22 technology (a technology utilized at the assignee of this application). A second design goal was that the architecture must work with both 8 bit data size and 16 bit data size memories as well as with DRAM memory. The address output from the 386 microprocessor is pipelined in some read/write cycles but in not all cycles. The microprocessor has an input pin called "NA" which acts as a request signal to the microprocessor to pipeline the address outputs for the next read/write cycle.
However, the integrated design did not have an extra pin to make NA available outside the chip. This means that the address outputs of the integrated design could not be pipelined outside the chip even if the microprocessor pipelines the addresses inside the chip. This required logic to be designed in the address output path to accommodate pipelining inside the integrated chip.
In addition, it was required that the integrated chip be able to provide row and column addresses directly to DRAM memory. This required logic needs to be designed in the address output path.
In order to test the core processor memory independently, it is required that the core address outputs be made directly available at pads in testmode (TSTMOD).
To accommodate all of these requirements a special address path design was necessary.
In addition, to achieve the fastest timing, a special scheme was developed to connect the onchip peripherals to different segments of the address path. Decoding addresses to determine if an eight bit or a sixteen bit memory was being addressed needed to be done as early as possible. Therefore, address decode logic was placed closest to the core address outputs. Since the core always executes as if 16 bit data size memory was being addressed, and since it was required for the integrated design to be able to work with 8 bit data size memories, it was necessary for a state machine to be added to create 2 cycles for each core read/write cycle when necessary to address an 8 bit data size memory.
It was also necessary to place the address decode logic for on-chip control registers closest to the core address outputs. This helped to make the control register read/write cycles in the least number of cpu clocks.